Analog Layout Engineer, Limerick

About Analog Devices

Analog Devices, Inc. (NASDAQ: ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible™. Learn more at and on and.

Analog Layout Engineer

The Sustainable Automation BU are seeking a motivated and creative Analog Layout Engineer to join our team developing Industry 4.0 leading silicon solutions to drive growth in our global business. The successful candidate will join a dynamic team in Limerick with excellent opportunities to work on leading edge development in Sustainable Industrial automation. Our diverse portfolio of products encompassing Industrial communication (eg Ethernet Phys and switches, IO-Link, ..) with configurable measurement and control (precision Analog and Digital I/O), which operate in harsh high voltage industrial domains and facilitates a wide variation of skill development and technology node experience. This position will afford the successful candidate the opportunity to participate in the development of large silicon systems working across multidisciplinary cross-functional teams including Analog and Digital Design, physical Implementation and CAD groups,. This is a senior level, hands-on, technical leadership position giving the opportunity to have great impact and influence on the SA team’s future direction.

Responsibilities include, but not limited to:

Layout ownership for full-chip and large-scale analog/mixed-signal blocks from floorplan through tapeoutFloorplan development at block, subsystem, and full-chip levels for designs of significant size and complexityTop-level integration of mixed-signal chips, including coordination between IP owners and digital physical design teams (as applicable)Schedule and milestone ownership for assigned layout scope, including resourcing and execution planning where applicablePhysical verification leadership, including DRC, LVS, ERC, antenna, density, extraction, and signoff documentationParasitic extraction coordination and support of post-layout simulation/debug to close performance targetsReliability and robustness closure, including EM/IR, ESD-aware layout, latch-up prevention, and isolation strategyAnalog layout best practices execution, including matching techniques, shielding, noise isolation, supply integrity considerations, and substrate/well strategyCross-functional partnership with circuit design, verification/validation, packaging, foundry, assembly, reliability, and failure analysis teams to enable design closureMethodology improvement, including development of checklists, templates, reusable collateral, and (where applicable) automation/scripting to reduce re-workTechnical leadership and mentoring for junior layout engineers; contribution to team standards and knowledge sharingTechnical communication, including clear reporting of status/risks, and preparation of supporting material for design reviews

Minimum qualifications

Bachelor’s degree in Electrical/Electronic/Computer Engineering (or related field) or equivalent experience10+ years of full-custom IC layout experience with analog/mixed-signal designs (block and/or full-chip)Proficiency with industry-standard custom layout tools and verification/signoff flowsProven ability to lead layout to signoff, including strong debug skills for physical verification issues and signoff closureProven expertise in analog layout fundamentals, including matching techniques, shielding/noise isolation, substrate/well strategy, latch-up prevention, and ESD-aware layoutDemonstrated ownership mindset: self-motivated, takes responsibility, and consistently closes complex layout problemsStrong planning and organizational skills (schedule/milestone ownership for assigned scope)Strong written and verbal communication skills; ability to produce clear supporting documentationDemonstrated ability to collaborate effectively across multi-discipline, multi-site global teams

Preferred Qualities

Experience as layout chip lead and/or top-level integration lead on large mixed-signal designsExperience in advanced CMOS nodesExperience with top-down integration methodologies, including AoT (Analog-on-Top) and DoT (Digital-on-Top) flowsExperience integrating large digital IP and partnering with digital physical design teamsExperience with high-voltage layout and/or BiCMOS technologiesScripting/automation experience (e.g., SKILL, PERL, AMPLE, or similar) to improve flow efficiency and qualityPCELL creation experienceTrack record of defining/improving layout methodologies, reusable IP, checklists, and documentation that measurably reduce re-workJob Req Type: ExperiencedRequired Travel: Yes, 10% of the timeShift Type: 1st Shift/Days